<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2258646</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar  9 19:08:29 2020</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.2 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>0c5a3c11c8a94cc28290b0b9cb8b87c9</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>69</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>f26330ce-68c6-468d-9895-870f944d4b15</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>f26330ce-68c6-468d-9895-870f944d4b15</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z020</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3192 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>34.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractfileview_reload=5</TD>
   <TD>abstractsearchablepanel_show_search=2</TD>
   <TD>addrepositoryinfodialog_ok=1</TD>
   <TD>addrepositoryinfodialog_repository_tree=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>addsrcwizard_specify_simulation_specific_hdl_files=1</TD>
   <TD>applyrsbmultiautomationdialog_checkbox_tree=1</TD>
   <TD>basedialog_apply=1</TD>
   <TD>basedialog_cancel=39</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=348</TD>
   <TD>basedialog_yes=35</TD>
   <TD>basereporttab_rerun=2</TD>
   <TD>clkconfigmainpanel_tabbed_pane=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>clkconfigtreetablepanel_clk_config_tree_table=38</TD>
   <TD>cmdmsgdialog_messages=2</TD>
   <TD>cmdmsgdialog_ok=38</TD>
   <TD>confirmsavetexteditsdialog_no=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>confirmsavetexteditsdialog_yes=1</TD>
   <TD>coretreetablepanel_core_tree_table=26</TD>
   <TD>createconstraintsfilepanel_file_name=1</TD>
   <TD>createsrcfiledialog_file_name=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>expruntreepanel_exp_run_tree_table=10</TD>
   <TD>filesetpanel_file_set_panel_tree=574</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=504</TD>
   <TD>fpgachooser_fpga_table=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>gensettingtreetablepanel_gen_setting_tree_table=45</TD>
   <TD>gettingstartedview_create_new_project=1</TD>
   <TD>graphicalview_zoom_fit=67</TD>
   <TD>hexceptiondialog_exit=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>ipstatussectionpanel_upgrade_selected=2</TD>
   <TD>mainmenumgr_edit=2</TD>
   <TD>mainmenumgr_file=10</TD>
   <TD>mainmenumgr_flow=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_project=4</TD>
   <TD>mainmenumgr_reports=4</TD>
   <TD>mainmenumgr_view=2</TD>
   <TD>mainmenumgr_window=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainwinmenumgr_layout=10</TD>
   <TD>messagewithoptiondialog_dont_show_this_dialog_again=2</TD>
   <TD>mioconfigtreetablepanel_mio_config_tree_table=5</TD>
   <TD>msgtreepanel_message_view_tree=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgview_information_messages=1</TD>
   <TD>msgview_warning_messages=1</TD>
   <TD>numjobschooser_number_of_jobs=1</TD>
   <TD>pacommandnames_auto_connect_target=25</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_close_rtl_design=3</TD>
   <TD>pacommandnames_create_top_hdl=3</TD>
   <TD>pacommandnames_goto_implemented_design=1</TD>
   <TD>pacommandnames_import_all_srcs=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_new_project=2</TD>
   <TD>pacommandnames_open_hardware_manager=15</TD>
   <TD>pacommandnames_open_in_new_window_rtl=1</TD>
   <TD>pacommandnames_open_rtl_design=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_ports_window=4</TD>
   <TD>pacommandnames_regenerate_layout=19</TD>
   <TD>pacommandnames_reload_rtl_design=4</TD>
   <TD>pacommandnames_reports_window=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_rtl_netlist_window=3</TD>
   <TD>pacommandnames_run_bitgen=19</TD>
   <TD>pacommandnames_selection_window=1</TD>
   <TD>pacommandnames_simulation_close=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_live_break=36</TD>
   <TD>pacommandnames_simulation_live_restart=24</TD>
   <TD>pacommandnames_simulation_live_run=98</TD>
   <TD>pacommandnames_simulation_live_step=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_run_behavioral=38</TD>
   <TD>pacommandnames_simulation_run_post_synthesis_functional=3</TD>
   <TD>pacommandnames_simulation_run_post_synthesis_timing=4</TD>
   <TD>pacommandnames_validate_rsb_design=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_zoom_fit=2</TD>
   <TD>paviews_address_editor=1</TD>
   <TD>paviews_code=52</TD>
   <TD>paviews_device=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_schematic=1</TD>
   <TD>paviews_system=1</TD>
   <TD>planaheadtab_refresh_ip_catalog=1</TD>
   <TD>programdebugtab_open_target=25</TD>
</TR><TR ALIGN='LEFT'>   <TD>programdebugtab_program_device=54</TD>
   <TD>programfpgadialog_program=55</TD>
   <TD>programfpgadialog_specify_bitstream_file=1</TD>
   <TD>progressdialog_background=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectnamechooser_project_name=1</TD>
   <TD>projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=4</TD>
   <TD>projecttab_reload=37</TD>
   <TD>rdicommands_delete=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_properties=1</TD>
   <TD>rdiviews_waveform_viewer=500</TD>
   <TD>removesourcesdialog_also_delete=2</TD>
   <TD>rsbapplyautomationbar_run_block_automation=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>rsbapplyautomationbar_run_connection_automation=2</TD>
   <TD>rungadget_show_error=1</TD>
   <TD>saveprojectutils_cancel=1</TD>
   <TD>saveprojectutils_save=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>selectmenu_highlight=1</TD>
   <TD>settingsdialog_project_tree=2</TD>
   <TD>settingsprojectiprepositorypage_add_repository=1</TD>
   <TD>settingsprojectiprepositorypage_refresh_all=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>signaltreepanel_signal_tree_table=40</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=5</TD>
   <TD>simulationliverunforcomp_specify_time_and_units=11</TD>
   <TD>simulationobjectspanel_simulation_objects_tree_table=116</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationscopespanel_simulate_scope_table=222</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3</TD>
   <TD>srcchooserpanel_create_file=4</TD>
   <TD>srcmenu_ip_documentation=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>stalemoreaction_out_of_date_details=1</TD>
   <TD>stalerundialog_open_design=1</TD>
   <TD>syntheticagettingstartedview_recent_projects=5</TD>
   <TD>syntheticastatemonitor_cancel=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuildermenu_add_ip=3</TD>
   <TD>systembuildermenu_create_port=1</TD>
   <TD>systembuildermenu_ip_documentation=1</TD>
   <TD>systembuilderview_add_ip=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuilderview_optimize_routing=22</TD>
   <TD>systembuilderview_orientation=1</TD>
   <TD>systembuilderview_pinning=7</TD>
   <TD>systemtab_report_ip_status=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>systemtab_upgrade_later=1</TD>
   <TD>systemtreeview_system_tree=7</TD>
   <TD>taskbanner_close=1</TD>
   <TD>tclconsoleview_tcl_console_code_editor=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>touchpointsurveydialog_no=1</TD>
   <TD>waveformnametree_waveform_name_tree=81</TD>
   <TD>waveformview_goto_last_time=1</TD>
   <TD>waveformview_goto_time_0=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>xpg_coefilewidgdet_browse=46</TD>
   <TD>xpg_ipsymbol_show_disabled_ports=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=7</TD>
   <TD>autoconnecttarget=25</TD>
   <TD>closedesign=3</TD>
   <TD>coreview=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>createblockdesign=2</TD>
   <TD>createtophdl=3</TD>
   <TD>customizecore=1</TD>
   <TD>customizersbblock=71</TD>
</TR><TR ALIGN='LEFT'>   <TD>editdelete=38</TD>
   <TD>editproperties=1</TD>
   <TD>fliptoviewtaskrtlanalysis=45</TD>
   <TD>launchprogramfpga=54</TD>
</TR><TR ALIGN='LEFT'>   <TD>newproject=3</TD>
   <TD>openblockdesign=66</TD>
   <TD>opendesign=1</TD>
   <TD>openhardwaremanager=45</TD>
</TR><TR ALIGN='LEFT'>   <TD>openinnewwindowrtlanalysis=1</TD>
   <TD>openrecenttarget=1</TD>
   <TD>recustomizecore=1</TD>
   <TD>regeneratersblayout=19</TD>
</TR><TR ALIGN='LEFT'>   <TD>reloaddesign=4</TD>
   <TD>reportipstatus=1</TD>
   <TD>runbitgen=76</TD>
   <TD>runimplementation=21</TD>
</TR><TR ALIGN='LEFT'>   <TD>runsynthesis=28</TD>
   <TD>savedesign=5</TD>
   <TD>savefileproxyhandler=2</TD>
   <TD>saversbdesign=35</TD>
</TR><TR ALIGN='LEFT'>   <TD>showview=12</TD>
   <TD>simulationbreak=36</TD>
   <TD>simulationclose=7</TD>
   <TD>simulationrestart=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrun=45</TD>
   <TD>simulationrunfortime=92</TD>
   <TD>simulationstep=1</TD>
   <TD>timingconstraintswizard=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>toolssettings=1</TD>
   <TD>ui.views.c.ap=1</TD>
   <TD>upgradeip=2</TD>
   <TD>validatersbdesign=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtaskipintegrator=3</TD>
   <TD>viewtaskprogramanddebug=2</TD>
   <TD>viewtaskprojectmanager=108</TD>
   <TD>viewtaskrtlanalysis=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtasksimulation=13</TD>
   <TD>zoomfit=2</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=9</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=15</TD>
   <TD>export_simulation_ies=15</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=15</TD>
   <TD>export_simulation_questa=15</TD>
   <TD>export_simulation_riviera=15</TD>
   <TD>export_simulation_vcs=15</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=15</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=43</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=10</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=2</TD>
   <TD>totalsynthesisruns=2</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>carry4=6</TD>
    <TD>fdce=268</TD>
    <TD>fdpe=31</TD>
    <TD>fdre=73</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=4</TD>
    <TD>ibuf=2</TD>
    <TD>ldce=9</TD>
    <TD>lut1=18</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2=104</TD>
    <TD>lut3=61</TD>
    <TD>lut4=57</TD>
    <TD>lut5=76</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6=386</TD>
    <TD>muxf7=45</TD>
    <TD>muxf8=18</TD>
    <TD>obuf=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=6</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>carry4=6</TD>
    <TD>fdce=268</TD>
    <TD>fdpe=31</TD>
    <TD>fdre=73</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=4</TD>
    <TD>ibuf=2</TD>
    <TD>ldce=9</TD>
    <TD>lut1=18</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2=104</TD>
    <TD>lut3=61</TD>
    <TD>lut4=57</TD>
    <TD>lut5=76</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6=386</TD>
    <TD>muxf7=45</TD>
    <TD>muxf8=18</TD>
    <TD>vcc=6</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bdsource=USER</TD>
    <TD>core_container=NA</TD>
    <TD>da_board_cnt=1</TD>
    <TD>da_clkrst_cnt=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>da_ps7_cnt=2</TD>
    <TD>iptotal=1</TD>
    <TD>maxhierdepth=0</TD>
    <TD>numblks=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>numhdlrefblks=0</TD>
    <TD>numhierblks=0</TD>
    <TD>numhlsblks=0</TD>
    <TD>numnonxlnxblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numpkgbdblks=0</TD>
    <TD>numreposblks=2</TD>
    <TD>numsysgenblks=0</TD>
    <TD>synth_mode=OOC_per_IP</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=BlockDiagram</TD>
    <TD>x_ipname=design_1</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=1.00.a</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dist_mem_gen_v8_0_12/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=10</TD>
    <TD>c_default_data=0</TD>
    <TD>c_depth=1024</TD>
    <TD>c_elaboration_dir=./</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_has_clk=0</TD>
    <TD>c_has_d=0</TD>
    <TD>c_has_dpo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_dpra=0</TD>
    <TD>c_has_i_ce=0</TD>
    <TD>c_has_qdpo=0</TD>
    <TD>c_has_qdpo_ce=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qdpo_clk=0</TD>
    <TD>c_has_qdpo_rst=0</TD>
    <TD>c_has_qdpo_srst=0</TD>
    <TD>c_has_qspo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qspo_ce=0</TD>
    <TD>c_has_qspo_rst=0</TD>
    <TD>c_has_qspo_srst=0</TD>
    <TD>c_has_spo=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_we=0</TD>
    <TD>c_mem_init_file=[user-defined]</TD>
    <TD>c_mem_type=0</TD>
    <TD>c_parser_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_pipeline_stages=0</TD>
    <TD>c_qce_joined=0</TD>
    <TD>c_qualify_we=0</TD>
    <TD>c_read_mif=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_a_d_inputs=0</TD>
    <TD>c_reg_dpra_input=0</TD>
    <TD>c_sync_enable=1</TD>
    <TD>c_width=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=dist_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2018.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pic16c56/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=2</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=user</TD>
    <TD>x_ipname=pic16c56</TD>
    <TD>x_ipproduct=Vivado 2018.2</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.3</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>pdrc-153=9</TD>
    <TD>rpbf-3=4</TD>
    <TD>zps7-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>ckld-2=1</TD>
    <TD>lutar-1=18</TD>
    <TD>timing-17=370</TD>
    <TD>timing-20=9</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_propagation=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vid=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=8to11 (8 to 11 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>confidence_level_clock_activity=Low</TD>
    <TD>confidence_level_design_state=High</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
    <TD>confidence_level_io_activity=Low</TD>
    <TD>confidence_level_overall=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
    <TD>devstatic=1.040901</TD>
    <TD>die=xc7z020clg400-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=9.983969</TD>
    <TD>effective_thetaja=11.5</TD>
    <TD>enable_probability=0.990000</TD>
</TR><TR ALIGN='LEFT'>    <TD>family=zynq</TD>
    <TD>ff_toggle=12.500000</TD>
    <TD>flow_state=routed</TD>
    <TD>heatsink=none</TD>
</TR><TR ALIGN='LEFT'>    <TD>i/o=4.388538</TD>
    <TD>input_toggle=12.500000</TD>
    <TD>junction_temp=125.0 (C)</TD>
    <TD>logic=2.837576</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtvccaux_dynamic_current=0.000000</TD>
    <TD>mgtvccaux_static_current=0.000000</TD>
    <TD>mgtvccaux_total_current=0.000000</TD>
    <TD>mgtvccaux_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>netlist_net_matched=NA</TD>
    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=11.024870</TD>
    <TD>output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_load=5.000000</TD>
    <TD>output_toggle=12.500000</TD>
    <TD>package=clg400</TD>
    <TD>pct_clock_constrained=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>pct_inputs_defined=0</TD>
    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
    <TD>ram_enable=50.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>ram_write=50.000000</TD>
    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>signals=2.757855</TD>
    <TD>simulation_file=None</TD>
    <TD>speedgrade=-2</TD>
    <TD>static_prob=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>temp_grade=commercial</TD>
    <TD>thetajb=7.4 (C/W)</TD>
    <TD>thetasa=0.0 (C/W)</TD>
    <TD>toggle_rate=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_board_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=11.5</TD>
    <TD>user_junc_temp=125.0 (C)</TD>
    <TD>user_thetajb=7.4 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_thetasa=0.0 (C/W)</TD>
    <TD>vccadc_dynamic_current=0.000000</TD>
    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccaux_dynamic_current=0.160668</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.099899</TD>
    <TD>vccaux_total_current=0.260567</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccbram_dynamic_current=0.000000</TD>
    <TD>vccbram_static_current=0.026492</TD>
    <TD>vccbram_total_current=0.026492</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccint_dynamic_current=5.599432</TD>
    <TD>vccint_static_current=0.298540</TD>
    <TD>vccint_total_current=5.897972</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_voltage=1.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco18_dynamic_current=0.000000</TD>
    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco33_dynamic_current=1.241011</TD>
    <TD>vcco33_static_current=0.001000</TD>
    <TD>vcco33_total_current=1.242011</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_voltage=3.300000</TD>
    <TD>vcco_ddr_dynamic_current=0.000000</TD>
    <TD>vcco_ddr_static_current=0.000000</TD>
    <TD>vcco_ddr_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_ddr_voltage=1.500000</TD>
    <TD>vcco_mio0_dynamic_current=0.000000</TD>
    <TD>vcco_mio0_static_current=0.000000</TD>
    <TD>vcco_mio0_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio0_voltage=1.800000</TD>
    <TD>vcco_mio1_dynamic_current=0.000000</TD>
    <TD>vcco_mio1_static_current=0.000000</TD>
    <TD>vcco_mio1_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio1_voltage=1.800000</TD>
    <TD>vccpaux_dynamic_current=0.000000</TD>
    <TD>vccpaux_static_current=0.010330</TD>
    <TD>vccpaux_total_current=0.010330</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpaux_voltage=1.800000</TD>
    <TD>vccpint_dynamic_current=0.000000</TD>
    <TD>vccpint_static_current=0.472757</TD>
    <TD>vccpint_total_current=0.472757</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpint_voltage=1.000000</TD>
    <TD>vccpll_dynamic_current=0.000000</TD>
    <TD>vccpll_static_current=0.003000</TD>
    <TD>vccpll_total_current=0.003000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpll_voltage=1.800000</TD>
    <TD>version=2018.2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=0</TD>
    <TD>bufgctrl_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=72</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=16</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=8</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=16</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=4</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=4</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=220</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=140</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=280</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=140</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=6</TD>
    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=266</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=31</TD>
    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=73</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=2</TD>
    <TD>ldce_functional_category=Flop &amp; Latch</TD>
    <TD>ldce_used=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=4</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=103</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=60</TD>
    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=57</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=76</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=384</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=45</TD>
    <TD>muxf8_functional_category=MuxFx</TD>
    <TD>muxf8_used=18</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=4</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=26600</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=45</TD>
    <TD>f7_muxes_util_percentage=0.17</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=13300</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=18</TD>
    <TD>f8_muxes_util_percentage=0.14</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=53200</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=586</TD>
    <TD>lut_as_logic_util_percentage=1.10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=17400</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=106400</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=370</TD>
    <TD>register_as_flip_flop_util_percentage=0.35</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=106400</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=9</TD>
    <TD>register_as_latch_util_percentage=&lt;0.01</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=53200</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=586</TD>
    <TD>slice_luts_util_percentage=1.10</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=106400</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=379</TD>
    <TD>slice_registers_util_percentage=0.36</TD>
</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=0.36</TD>
    <TD>fully_used_lut_ff_pairs_used=5</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=53200</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=586</TD>
    <TD>lut_as_logic_util_percentage=1.10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=17400</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=0</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=67</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=67</TD>
    <TD>lut_ff_pairs_with_one_unused_lut_output_used=59</TD>
    <TD>lut_flip_flop_pairs_available=53200</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=76</TD>
    <TD>lut_flip_flop_pairs_util_percentage=0.14</TD>
    <TD>slice_available=13300</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_used=251</TD>
    <TD>slice_util_percentage=1.89</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=91</TD>
    <TD>unique_control_sets_used=97</TD>
    <TD>using_o5_and_o6_fixed=97</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=98</TD>
    <TD>using_o5_output_only_fixed=98</TD>
    <TD>using_o5_output_only_used=0</TD>
    <TD>using_o6_output_only_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=488</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>actual_expansions=439578</TD>
    <TD>bogomips=0</TD>
    <TD>bram18=0</TD>
    <TD>bram36=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
    <TD>bufr=0</TD>
    <TD>ctrls=97</TD>
    <TD>dsp=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>effort=2</TD>
    <TD>estimated_expansions=752556</TD>
    <TD>ff=379</TD>
    <TD>global_clocks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>high_fanout_nets=0</TD>
    <TD>iob=6</TD>
    <TD>lut=591</TD>
    <TD>movable_instances=1145</TD>
</TR><TR ALIGN='LEFT'>    <TD>nets=1163</TD>
    <TD>pins=6260</TD>
    <TD>pll=0</TD>
    <TD>router_runtime=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>router_timing_driven=1</TD>
    <TD>threads=2</TD>
    <TD>timing_constraints_exist=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7z020clg400-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:22s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=509.871MB</TD>
    <TD>memory_peak=790.875MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=post-synthesis</TD>
    <TD>-sim_type=functional</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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